USB4 Gen3 x2-lane PHY, TSMC 12FFC, 1.8V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
- USB4
- TSMC
- 12nm
- FFC
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB4 Gen3 x2-lane PHY, TSMC 12FFC, 1.8V, N/S orientation, type-C
The USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
USB-C 3.2 DP/TX PHY in TSMC (N3E)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
USB-C 3.2 DP/TX PHY ebdaux in TSMC (N5)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
The 224G Ethernet PHY IP, an integral part of the high-speed SerDes IP portfolio, meets the growing high bandwidth and low latenc…
TSMC N4P SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N5 SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
The IP is a USB PHY based on TSMC 180nm process.
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.