Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 65nm
- LP
- Available on request
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable…
TSMC N3P SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
12G Ethernet PHY, TSMC 28HPC x1 North/South orientation
The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
12G Ethernet PHY, TSMC 28HPC x1 North/South orientation
The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
USB-C 3.2 DP/TX PHY in TSMC (N3E)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
USB-C 3.2 DP/TX PHY ebdaux in TSMC (N5)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
The IP is a USB PHY based on TSMC 180nm process.
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…