Vendor: Synopsys, Inc. Category: Single-Protocol PHY

TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

Overview

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations. It includes an optional digi logic circuitry which is required for high-speed operations. It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards.

Key features

  • Completely hardened PHY solution along with programmable delay chains & I/Os
  • Fully selectable output impedance
  • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
  • Automotive G1/G2 supported, ASIL-B certified
  • Interoperability checks done with Synopsys Controllers
  • HBM 2KV, CDM 500V(up to 7A), Latch-up +/-100 mA @ 125C
  • Silicon validated IP
  • Designed to support multiple metal stack options
  • Support for flip-chip & wirebond packaging

Silicon Options

Foundry Node Process Maturity
TSMC 5nm N5 —

Specifications

Identity

Part Number
dwc_io_ts5ff_1p8v_emmc_sd_phy_ms
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

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Provider

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks?

TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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