IO pad library IP provides the physical interface between internal core logic and external chip pins. These libraries are critical for signal integrity, ESD robustness, voltage domain interoperability, manufacturability, and reliable chip-level integration across semiconductor products.
Explore IO pad IP libraries including GPIO, analog pads, high-speed pads, and protection structures tailored to foundry process requirements.
TSMC 40LP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) p…
TSMC 40LP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designe…
Library of LVDS IOs cells for TSMC 40LP
The nSIO2000_TS40LP_2V5_1V1 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.1V or…
TSMC 40G Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) p…
TSMC 40G 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designe…
TSMC 40G 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC …
TSMC 40G 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 …
Library of LVDS IOs cells for TSMC 40G
The nSIO2000_TS40G_2V5_0V9 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/0.9V or …
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to …
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin E…
Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet …
Output Buffer for up to 12Gb/s
The PMCC_OBUF12G is a differential CML 50Ω terminated output driver for datarates from DC up to 12Gb/s.
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/…
ESD diode and Clamps for 90nm TSMC G/GT/LP
Stand alone ESD diodes and Supply clamping for TSMC 90nm G/GT/LP processes
TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
This TSMC 3nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.
TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins.
TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins.