Vendor: Archband Labs Inc. Category: Analog

Programmable Special IO in SMIC0.13um

AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/…

Overview

AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extremely suitable for FPGA/MPGA design where special IO functions are desired to meet customers' various requirements.

Key features

  • Programmable IO with Customized Layout Design
  • ESD Safe IO Pad
  • Support LVDS, LVTTL
  • Support LVCMOS-33/25/18/15
  • Support SSTL_3/2/18

Benefits

  • Ready to be implimented in SoC or FPGA/MPGA design
  • Reduce development time
  • Flexible in application
  • Portable to other process node

What’s Included?

  • Full Datasheet
  • Application Note
  • Integration Guidance
  • Behavior Model
  • GDSII Abstract (.LEF Format)
  • Timing Library (.LIB Format)
  • LVS Netlist (SPICE Compatible)
  • Physical Design Database (GDSII Format)
  • Silicon Validation Report
  • AE Support

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G

Specifications

Identity

Part Number
AR750S13
Vendor
Archband Labs Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Analog I/O Pad Library IP cores

What is Programmable Special IO in SMIC0.13um?

Programmable Special IO in SMIC0.13um is a Analog IP core from Archband Labs Inc. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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