AI-Generated UVM Testbenches from SoC Specifications
This article explains why building testbenches by hand is so slow, why the specification is the right place to start, and what an AI-generated flow looks like in practice.
Vendor:
Agnisys, Inc.
Category:
Bus Fabric
Crossbars Interconnect
An interconnect component connects initiators and targets in a system.
Overview
An interconnect component connects initiators and targets in a system. A single initiator system simply requires a decoder and multiplexor, which are explained in the following sections. In a multi-initiator system, an interconnect is necessary for signal routing and arbitration between initiators to the proper target. This route is necessary for address, control, and write data signals. This specification does not include the specific methodologies implemented for multi-initiator systems, including single or multi-layer interconnects.
Key features
- APB
- N X M Where N stands for initiators and M stands for targets.
- AHB
- N X M Where N stands for initiators and M stands for targets.
- Maximum initiators can be 16 as per AMBA-AHB specification.
- AXI
- N X M Where N stands for initiators and M stands for targets.
- Maximum initiators can be 16 as per AMBA-AXI specification.
Specifications
Identity
Part Number
Crossbars Interconnect
Vendor
Agnisys, Inc.
Type
Silicon IP
Provider
HQ:
USA
Learn more about Bus Fabric IP core
How IDS-AI Helps Make Your Specifications Golden
Discover how IDS-AI simplifies specification checking to create Golden Specifications and generate reliable outputs for your SoC and IP development workflows.
How to Make Your Specifications Golden
Learn how to create golden specifications for SoC and IP designs with IDS-AI by ensuring completeness, accuracy, consistency, traceability, and faster design automation.
Mastering Semiconductor Chip Design: Tools, Techniques, and Best Practices
Explore how EDA tools and specification automation simplify chip design, verification, software development, and SoC validation while improving quality.
Agnisys and Axiomise Collaborate to Accelerate NoC Design and Formal Sign-off
Agnisys and Axiomise partner to pair IDS-NoC™ automated NoC generation with nocProve® formal verification for AI, GPU, and inference chip designs.
Automated, Faster Specification to Sign-Off with IDS-AI
IDS-AI is the industry’s first agentic AI framework built specifically for semiconductor development. It understands your design functional specification, your control and status registers (CSRs), your programming sequences, your system-on-chip (SoC) hierarchy, and your block interconnections.
Frequently asked questions about On-Chip Bus IP cores
What is Crossbars Interconnect?
Crossbars Interconnect is a Bus Fabric IP core from Agnisys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.