Vendor: Codasip Category: CPU

RISC-V processor - 32 bit, 5-stage pipeline

The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requ…

RISC-V View all specifications

Overview

The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating point unit.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L50 or L50F and to generate corresponding hardware and software development kits.

Key features

  • 32-bit RISC-V core
    • The L50 supports the RV32IMC ISA
    • The L50F supports the RV32IMCF ISA
  • Fully parallel multiplier
  • 5-stage pipeline
  • Dynamic Branch Predictor
  • RISC-V privilege mode support:
    • Machine, User
  • Internal interrupt controller
    • Up to 256 sources
  • Optional FPU (L50F)
  • Optional instruction and data tightly coupled memories (TCM)
  • Optional 8 or 16 PMP regions
  • Optional L1 data and instruction caches
  • On-chip debugger
    • JTAG and RISC-V Debug module

Benefits

  • Flexibility
    • Wide choice of configuration options.
  • Customization
    • Ability to create custom RISC-V extensions to optimise performance
    • Efficient architectural exploration of custom extensions with Studio
    • Automatic HDK and SDK generation from Studio
    • Rigorous verification of modified L50(F) core using UVM

Applications

  • The L50 core is suitable for embedded applications requiring medium processing performance and a higher clock frequency.

What’s Included?

  • Human-readable and structured RTL in either:
    • Verilog
    • VHDL
    • System Verilog
  • Hardware development kit (HDK)
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • LLVM C-compiler
    • Assembler
    • Disassembler
    • Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
  • Option for extending L50
    • CodAL model for Codasip Studio
    • Full-feature Studio tool for extending Bk5 core
    • GUI for rapid development and debugging
    • Automatic HDK & SDK generation

Specifications

Identity

Part Number
Codasip L50(F)
Vendor
Codasip
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Codasip
HQ: Germany

Learn more about CPU IP core

Codasip announces strategic pivot and divestiture

Codasip today announced a strategic evolution of its business to focus on the rapidly growing need for cyber-resilient semiconductor architectures and semiconductor System on Chips (SoCs). In conjunction with this change, Codasip is also announcing the divesture of its low-end RISC-V processor design business to a public US semiconductor company.

Codasip board initiates an expedited process to sell the company

Codasip, the European RISC-V leader, announced today an accelerated process to sell the company. Codasip has been awarded several grants and equity funding from various bodies of the European Union (EU) and national authorities totaling over €119 million, most of which is still to be received by the company in due course. In addition, the company estimates the follow-on phases of the grants will total a further €210 million for a total of €329 million, and the company is part of new consortiums and projects that can bring in an additional €51 million or more in future financing.

Frequently asked questions about CPU IP cores

What is RISC-V processor - 32 bit, 5-stage pipeline?

RISC-V processor - 32 bit, 5-stage pipeline is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

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