Vendor: Xilinx, Inc. Category: Channel Coding

Soft-Decision FEC Integrated Block

For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is …

Contact Provider Request Datasheet

Overview

For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access,  transmission reliability is a key success factor to support the quality of the overall system. A high performance Soft-Decision FEC (i.e. >1Gbps), is a major building block used to enable these systems to function under non-ideal environments.

The Soft-Decision Forward Error Correction (SD-FEC) integrated block supports Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding. The LDPC codes used are highly configurable, and the specific code used can be specified on a codeword-by-codeword basis.   

Key features

  • Function configurable between either:
    • LDPC decode or encode of a range of customer specified Quasi-cyclic (QC) codes, or
    • Turbo decode of codes used by LTE
  • Peak throughput of the order:
    • 1.78 Gb/s Turbo decode @ 6 iterations
    • 3.03 Gb/s for LDPC Decode @ 8 iterations
    • 20.34 Gb/s for LDPC Encode
    • Scalable implementation
      • Multiple instantiations on a device (not all cores supported simultaneously in LDPC and Turbo modes)
    • High bandwidth AXI4-Stream interfaces
    • Support for customer programming of class of LDPC code
    • Significant FPGA resource savings compared to a soft IP implementation
    • Overall reduced system power with up to 2x the performance
    • Dynamically optimize and configure parameters for evolving 5G standards

Specifications

Identity

Part Number
Soft-Decision FEC Integrated Block
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is Soft-Decision FEC Integrated Block?

Soft-Decision FEC Integrated Block is a Channel Coding IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP