Embedded Systems: Programmable Logic -> Reusable models trim software costs
Embedded Systems: Programmable Logic -> Reusable models trim software costs
Vendor:
Nagase & Co., Ltd.
Category:
Control Logic
Extremely Low Latency Matching Engine Synthesizable IP Core
Axonerve is a next generation variant of the content-addressable memory (CAM) solution.
Overview
Axonerve is a next generation variant of the content-addressable memory (CAM) solution. Its unique algorithmic matching engine realizes high-speed & low-latency content matching at ultra-low power consumption.
Axonerve can perform continuous search operation with extremely low latency and achieve 150MSPS to track 100Gbps network packets. It can support exact and wildcard matching for N-tuple header fields. It also provides a priority function that determines which one should be finally selected out of multiple matches. You don’t need to sort or update a whole entry table any more to change the matching order.
Axonerve is a fully-synthesizable IP core. It adopts common 6T-SRAM technology and requires no special memory structure design. It leads to power and area saving, and enables you to implement single or multiple instances of Axonerve IP cores in FPGA as well as ASIC.
Axonerve can perform continuous search operation with extremely low latency and achieve 150MSPS to track 100Gbps network packets. It can support exact and wildcard matching for N-tuple header fields. It also provides a priority function that determines which one should be finally selected out of multiple matches. You don’t need to sort or update a whole entry table any more to change the matching order.
Axonerve is a fully-synthesizable IP core. It adopts common 6T-SRAM technology and requires no special memory structure design. It leads to power and area saving, and enables you to implement single or multiple instances of Axonerve IP cores in FPGA as well as ASIC.
Key features
- Key length
- 144/288/576/1152 bits
- Entry capacity
- 1M entries / 288[bit] (*)
- Search latency
- 10 cycles (on-chip memory mode)
- TBD cycles (off-chip memory model)
- Search speed
- 150MSPS @150MHz
- Operations
- Entry write/read/delete/update
- Aging operations (optional)
- OpenFlow friendly
- Field masking for N-tuple header field
- Priority setting for every entry
- 28nm process silicon proven
Block Diagram
Axonerve block diagram
Applications
- SDN/OpenFlow switch
- L2 MAC lookup
- Deep packet inspection
- Carrier grade NAT
- Memcached server
- Dedup storage
- Virus signature matching
- IoT data mining
- Key-value Store (KVS)
Specifications
Identity
Part Number
Axonerve
Vendor
Nagase & Co., Ltd.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Japan
Learn more about Control Logic IP core
OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
This work presents OpenEye, a scalable and sparsity-aware FPGA-based hardware accelerator designed to efficiently execute common neural network operations such as convolutions, dense layers, and pooling.
AES in embedded systems: Understanding the most important AES modes
Explore key AES modes in embedded systems, their applications, and why selecting the right mode is crucial for security and efficiency in modern designs.
Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
Explore the differences between SHA-2 and SHA-3 for embedded systems, focusing on performance, design, and integration.
A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)
This article provides an in-depth analysis of the specific PPA challenges introduced by PQC and elucidates how PUF-PQC leverages its unique dualtrack strategy to deliver a robust and flexible Hardware Root of Trust (HRoT) across diverse application scenarios. Furthermore, it demonstrates the integration of Physical Unclonable Function (PUF) with a NIST SP 800-90B compliant True Random Number Generator (TRNG) to serve as critical components of PUFrt (Root of Trust), ensuring the security of post-quantum key generation starting from the entropy source.
The Power of Shifting Left: Cadence Accelerating Innovation with Arm
In semiconductor design, projects are remembered for their extremes—legendary successes and cautionary failures. The difference often hinges on when problems are discovered. A bug found late in development can derail timelines and budgets. This is why "shifting left"—moving testing and validation earlier in the process—is now a critical strategy for innovation.
Frequently asked questions about Control Logic Accelerator IP cores
What is Extremely Low Latency Matching Engine Synthesizable IP Core?
Extremely Low Latency Matching Engine Synthesizable IP Core is a Control Logic IP core from Nagase & Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Control Logic?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Control Logic IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.