The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
- Channel Coding
- In Production
- Immediate
- yes
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC).
5G NR is the mobile broadband standard of the 5th generation.
Generic Polar FEC Encoder and Decoder
Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communicati…
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
DVB-S2X Wideband BCH and LDPC Decoder
The DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on FPGAs.
CCSDS AR4JA LDPC Encoder & Decoder
The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
DisplayPort 1.4 FEC Receiver (Rx)
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream.
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
LTE and LTE (LTE-A) are the mobile broadband standard of the 4th generation.
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.
IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
DVB-RCS (Digital Video Broadcasting – Interaction channel for satellite distribution systems) is an established ETSI standard for…
IEEE 802.11ad (WiGig 60GHz) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard …