S2C Named Andes Technology’s 2026 Partner of the Year

Companies to demonstrate AndesCore™ AX66 RISC-V processor running Linux KVM virtualization and AI inference on S2C’s Prodigy™ S8-100 at AI Infra Summit

San Jose, Calif. — September 17, 2026 — S2C, a leading provider of FPGA-based prototyping solutions for ASIC and SoC development, today announced that it has been named 2026 Partner of the Year by Andes Technology a premier supplier of RISC-V processor IP and a Founding Premier member of RISC-V International. The recognition reflects a year of expanded collaboration between the two companies to help RISC-V SoC teams validate processor IP, software stacks, and AI application scenarios earlier in the design cycle.

S2C and Andes are showcasing the collaboration at the AI Infra Summit, September 15–17 at the Santa Clara Convention Center, where Andes will demonstrate its high-performance AndesCore™ AX66 RISC-V processor running live on S2C’s Prodigy™ S8-100 prototyping system at Booth #1704.  

Live Demonstration at Booth #1704: Accelerating Pre-Silicon AI Architecture Decisions

The AndesCore™ AX66 is Andes’ flagship 64-bit RISC-V application processor IP compliant with the RVA23 profile. The AX66 features a 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution. It supports Vector and Vector Crypto extensions, Hypervisor extension with AIA, and multi-cluster configurations over CHI for high-performance Linux and Android applications.

At Booth #1704, Andes will showcase a quad-core AX66 cluster mapped onto a single AMD Versal™ Premium VP1902 FPGA within S2C’s Prodigy S8-100 system. The demonstration will operate at 60 MHz and use approximately 55% of the FPGA logic capacity. The live setup will feature:

• Linux KVM Virtualization: Boots a hypervisor environment hosting two separate virtual machines.
• Live AI Inference: Runs two lightweight large language models, TinyStories 42M based on Llama 2 architecture, simultaneously in the virtualized environment.

For RISC-V SoC design teams, this demonstration addresses an important pre-silicon challenge: validating that custom instruction-set extensions, such as Andes Custom Extension, and hardware accelerators can boot full software stacks, including hypervisors and AI workloads, at meaningful performance levels before tape out. By moving these evaluations onto a live FPGA prototype, engineering teams can reduce delays from late‑stage silicon availability and make critical architecture decisions earlier in the development cycle.

“Prototyping is no longer just a late-stage verification tool; it is where critical software and architecture decisions are proven early,” said Ying Chen, VP of S2C. “Running Linux KVM and dual LLM workloads on the S8-100 gives Andes’ customers actionable, real-world data for their architectural analysis and decisions. We are honored to receive the Partner of the Year award. It reflects a powerful synergy between Andes’ leading silicon IP and S2C’s scalable prototyping platform, supported by our global engineering presence.”

“Our partnership with S2C has provided our customers with a clear, reliable path to validate complex software stacks on our high-performance RISC-V cores long before silicon availability,” said Dr. Charlie Su, President and CTO of Andes Technology. “S2C’s robust FPGA prototyping hardware and global support network have been a key in expanding the reach of our AX66 and vector processor IP across global markets.”

A Global, Repeatable Joint Showcase Model

The 2026 Partner of the Year award reflects a sustained, collaborative effort throughout the year, including: 

• RISC-V Now! by Andes 2026: Co-presentations and live hardware demonstrations across Hsinchu, San Jose, Beijing, and Shanghai.
• COMPUTEX 2026 & DVCon Series: Flagship showcases in Taiwan, Japan, and North America.
• RISC-V Summits: Technical engagement at the RISC-V Summit North America and the upcoming RISC-V Summit China.

S2C’s global presence, spanning seven offices and service centers, enables Andes and its customers to deploy repeatable prototyping setups with local engineering support across regions. This joint showcase model helps accelerate design-win cycles for Andes while giving S2C customers reusable IP validation frameworks and regionally supported prototyping setups. 

Explore Andes IP:

• RVA23, Multi-cluster, Hypervisor and Android
• 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
• Superscalar Out-of-Order Execution Multicore Cluster
• 64-Bit 8-stage superscalar RISC-V processor
• 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

Looking Ahead

As RISC-V architecture expand into data center and AI infrastructure markets, the connection between silicon IP and FPGA-based prototyping is becoming increasingly important. Following the AI Infra Summit, S2C and Andes plan to present the AX66-on-S8-100 demonstration at RISC-V Summit China, Oct. 18–20, with further joint ecosystem initiatives planned through the end of 2026.

About S2C

S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 700 customers, including 11 of the world’s top 25 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customers’ SoC and ASIC verification requirements. S2C has offices and sales representatives in San Jose, Seoul, Tokyo, Shanghai, Hsinchu, India, Europe and ANZ.

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 20 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com.