SoC low-power verification requires a full-chip solution
Thomas L. Anderson Vice President of Marketing Breker Verification Systems, Inc.
EETimes (4/13/2012 11:20 AM EDT)
Not too long ago, low-power design was an esoteric discipline practiced mostly by makers of digital watches and calculators. In the last 20 years, a steady series of new products that run on batteries for much of their lives has brought the need for power conservation to the forefront of the electronics business. Cell phones, smart phones, tablets, and other consumer devices have sophisticated, power-hungry processors and wireless links. Further, “green” laws and industry initiatives have mandated lower power even for “big iron” servers, switches, and telephony equipment.
At the heart of all these products are system-on-chip (SoC) designs combining one or more embedded processors with a variety of functional units, all interconnected by some type of bus or fabric. There is a wide range of techniques used to reduce the power consumed by these SoCs, including innovative transistor and cell designs, substrate biasing, and varying voltages. These have no significant effect on verification of the system model or the RTL design. However, the technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). Shutting off functional units not currently needed clearly saves both leakage current and dynamic power.
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