DAC 2024 - Showcasing the future of RISC-V through EDA
Brett Cline, Codasip
Vendor:
Renesas
Category:
DAC
Dual Channel 12b D/A Converter - TSMC T40ULP+ESF3
A Dual Channel 12b D/A converter are provided with TSMC T40ULP+ESF3 wafer process
Overview
A Dual Channel 12b D/A converter are provided with TSMC T40ULP+ESF3 wafer process. They are voltage output D/A Converter, supporting the wide supply range from 1.62 to 3.63V. The reference voltage can be set independently on the power supply. The linearity is excellent and the transition is fast. They support 2 operation choices; at the 1st mode; high buffered mode, they can drive 50pF capacitive load and 5k-ohm resistive load. And at the 2nd mode; high accuracy mode, they can show the high linearity from 0 to FS
Key features
- 12b resolution, 3µs conversion time
- Level Shifter inside. Directly connectable Interface to the digital section.
- Dual channel
- Independent Reference Voltage from the power supply
- Support 2 output mode; highly drivable mode / highly accurate mode.
- High Drivability of 50pF capacitive load and 5k-ohm resistive load at the highly drivable mode.
- Excellent linearity from 0 to FS at the accurate mode.
Block Diagram
Click to open fullscreen
1 /
2
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | ULP | Available on request |
Specifications
Identity
Part Number
2ch 12-bit R-2R DAC with buffer (3µs)
Vendor
Renesas
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Japan
Learn more about DAC IP core
Making the most of the 60th DAC
Brett Cline, Codasip
DAC 2022 - Is it too risky not to adopt RISC-V?
Brett Cline, Codasip
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
DAC: The View from Wall Street
DAC Panelists Discuss Emulation's Versatility & Various Use Models
Lauro Rizzatti, Verification Consultant
Frequently asked questions about DAC IP cores
What is Dual Channel 12b D/A Converter - TSMC T40ULP+ESF3?
Dual Channel 12b D/A Converter - TSMC T40ULP+ESF3 is a DAC IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this DAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.