A Dual Channel 12b D/A converter are provided with TSMC T40ULP+ESF3 wafer process
The AT4UFDAC00001235DDAFA0 is a dual-channel, 12-bit digital-to-analog converter (D/A) IP fabricated using TSMC's T40ULP+ESF3 (40nm Ultra-Low Power with Embedded SuperFlash 3) wafer process.
This voltage output D/A converter supports a wide supply range from 1.62V to 3.63V. The reference voltage can be set independently on the power supply. The linearity is excellent, and the transition is fast. The device supports two operation choices—high buffered mode, in which it can drive a 50pF capacitive load and a 5kΩ resistive load, and a high accuracy mode, in which it can show the high linearity from 0 to Full-Scale (FS).
Electrical Characteristics
| Item | Unit | Spec MIN | Spec TYP | Spec MAX | Description |
|---|---|---|---|---|---|
| Power Supply AVCC | V | 1.62 | - | 3.63 | |
| Power Supply VDD | V | 0.81 | - | 1.21 | |
| Temperature | °C | -40 | 25 | 125 | |
| Output Range — highly drivable mode | V | 0.2 | - | AVCC-0.2 | |
| Output Range — highly accurate mode | V | 0 | - | AVCC | |
| Conversion time | µs | - | - | 3 | |
| Integral Non-Linearity (INL) | LSB | -4 | - | +4 | |
| Differential Non-Linearity (DNL) | LSB | -1 | - | +1 | |
| Center Offset Error at highly drivable mode | LSB | -20 | - | +20 | |
| Gain Error at highly drivable mode | % | -1 | - | +1 | |
| Power consumption — highly drivable mode | mA | - | 2.6 | - | |
| Power consumption — highly accurate mode | mA | - | 0.25 | - | |
| Area | mm² | 0.113 | size on Si | ||
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | ULP | Available on request |
Note: some files may require an NDA depending on provider policy.
2-Channel, 12-Bit, R-2R Digital-to-Analog Converter IP with Buffer (3µs) is a DAC IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
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