AXI External Memory Controller
The AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…
- Controller
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
AXI External Memory Controller
The AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target…
The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use wit…
The AXI BRAM Controller is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK) and Vivado™ IP Integrator…
The axi2axi_connector is a utility module for use in EDK to cascade two AXI Interconnect modules.
The AXI ( eXtensible Interface) to APB ( Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions.
Triple-Rate SDI on Virtex-6 FPGAs
The Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital …
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
Xilinx provides a market DPD solution that reduces CapEx and OpEx Digital Pre-Distortion (DPD) is one of the most fundamental bui…
The 3GPP LTE Channel Estimator LogiCORE™ IP provides an optimized channel estimation function for the Physical Uplink Shared Chan…
4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)
PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps.
Low noise PLL operating at up to 3.25GHz (90nm UMC)
PSI3GRP_U9 is a low jitter PLL operating from 1GHz to 3.25GHz.
Wide range PLL operating from 135MHz to 945MHz (90nm UMC)
PSIWRP_U9 is a wide range PLL with the VCO operating from 175MHz to 945MHz.
Low spurs PLL operating at 1.296GHz (90nm UMC)
PSI1GLSP_U9 is a low spurs PLL operating at 1.296GHz.
Low noise PLL operating at 1.25GHz and 625MHz (90nm UMC)
PSI1GLP_U9 is a low jitter PLL operating at 1.
Low noise PLL operating at up to 5GHz (40nm TSMC)
PSI5GLP_T4 is a low jitter PLL operating from 3GHz to 5GHz continuously, and with the output divider it can cover 1/2 and 1/4 spe…
Low noise PLL operating at up to 3.25GHz (40nm TSMC)
PSI3GLP_T4 is a low jitter PLL operating from 2GHz to 3.3GHz continuously, and with the output divider it can cover 1/2 and 1/4 s…