What is Low noise PLL operating at up to 3.25GHz (40nm TSMC)?
Low noise PLL operating at up to 3.25GHz (40nm TSMC) is a PLL IP core from Pico Semiconductor, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
Vendor:
Pico Semiconductor, Inc.
Category:
PLL
Low noise PLL operating at up to 3.25GHz (40nm TSMC)
PSI3GLP_T4 is a low jitter PLL operating from 2GHz to 3.3GHz continuously, and with the output divider it can cover 1/2 and 1/4 s…
Overview
PSI3GLP_T4 is a low jitter PLL operating from 2GHz to 3.3GHz continuously, and with the output divider it can cover 1/2 and 1/4 speed. PSI3GLP_T4 can be used for a wide range of applications in SERDES transceivers such as XAUI, RXAUI, SGMII, HRIF, SFI, SATA, SAS, FC. It can also be used in many other applications for clock generation.
Key features
- Low jitter PLL for a wide range of applications
- Output frequencies 2-3.3GHz, 1-1.65GHz and 500-825MHz
- Reference clock 50-800MHz
- Power supplies 0.9V and 1.2V
- TSMC 40nm G
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | G | — |
Specifications
Identity
Part Number
PSI3GLP_T4
Vendor
Pico Semiconductor, Inc.
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.