What is Low noise PLL operating at up to 3.25GHz (90nm UMC)?
Low noise PLL operating at up to 3.25GHz (90nm UMC) is a PLL IP core from Pico Semiconductor, Inc. listed on Semi IP Hub. It is listed with support for umc.
Vendor:
Pico Semiconductor, Inc.
Category:
PLL
Low noise PLL operating at up to 3.25GHz (90nm UMC)
PSI3GRP_U9 is a low jitter PLL operating from 1GHz to 3.25GHz.
Overview
PSI3GRP_U9 is a low jitter PLL operating from 1GHz to 3.25GHz. PSI3GRP_U9 can be used for a wide range of applications in SERDES transceivers such as XAUI, RXAUI, SGMII, SATA, SAS, FC. It can also be used in many other applications for clock generation.
Key features
- Low jitter PLL for a wide range of applications
- Output frequencies 1-3.25GHz.
- Reference clock 100-156.25MHz
- Power supply 1.2V
- UMC 90nm SP
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 90nm | SP | — |
Specifications
Identity
Part Number
PSI3GRP_U9
Vendor
Pico Semiconductor, Inc.
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.