VESA introduced the first Display Stream Compression (DSC) standard in 2014.
- VESA DSC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors.
MIPI M-PHY® 4.1 Analog Transceiver
MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
Host / device LIN controller IP
The LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications.
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…
Arasan Chip Systems is a System on Chip (SoC) Intellectual Property (IP) provider of a suite of Mobile Industry Processor Interfa…
scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface ORAN IP core is a scalable and…
E-Series GPU IP delivers fast and flexible parallel compute that scales from wearables to the cloud.
DeepMentor has developed an AI IP that combines low-power and high-performance features with the RISC-V SOC.
The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s.
7 Bit 6 GS/s Folding ADC on Fujitsu 55 nm CS250L
The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
SONET/SDH OC-3 Transceiver/CDR
The SMS2011 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
The Stealth AES Encryption IP provides encryption capabilities to secure data transmission and storage in various applications, i…
Lithe Layer 2 Gigabit Ethernet Switching IP
The Lithe Layer 2 Gigabit Ethernet Switching IP is a comprehensive solution for building scalable and efficient network infrastru…
Lightweight, Scalable Cryptographic Accelerators for Secure SoC Designs The Cryptographic Cores IP portfolio delivers secure, hig…
ULP Clock Generator - GLOBALFOUNDRIES 22FDX
ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in energy efficient Systems on Chip.
scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 The MIPI CSI-2 IP core is a scalab…
The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interfa…
Unveiling the Magic of JPEG XS Meet JPEG XS, a revolutionary solution that redefines how you handle video content.