MIPI CSI-2 IP

Highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1

The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the  MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies. The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.

Optimized for performance, flexibility, and minimal resource utilization, this IP supports various applications, including mobile, automotive, industrial vision, and embedded systems. It supports advanced features like Smart Region of Interest (SROI), Always-On Sentinel Conduit (AOSC), and RGB, YUV and RAW data types and JPGEG format and Raw Data Compression, enhancing versatility in real-time imaging and machine vision systems.

With scalable lane support and seamless integration into FPGA and ASIC environment. The IP comes with the widest parameter set available and has gone through extensive testing in our UVM regression test environment.

• Supports:
  • (SROI) Smart Region of Interest,
  • (USL) Universal Serial Link,
  • (AOSC) Always-On Sentinel Conduit,
  • (MPC) Multi-Pixel Compression
• Integrates Easily with C-PHY and D-PHY through the MIPI PPI Interface
• Support for all Data Types and Compression Modes
• Silicon Agnostic

• Test Environment: CSI-2 IP is Tested in UVM regression for full functional coverage
• Silicon Agnostic: Designed in Verilog and targeting ASICs and FPGAs
• System Integration: Integration support with C-PHY / D-PHY components for quick and efficient  deployment
• Active Support: All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format.
• The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request