The designated IP is a power on reset circuit intended for integration into 130nm CMOS technology System on Chips.
- Power On Reset (POR)
- Silicon Implemented
- Immediate
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The designated IP is a power on reset circuit intended for integration into 130nm CMOS technology System on Chips.
The designated IP is a very low power, high precision band gap reference circuit intended for integration into 130nm CMOS technol…
Low power 8-bit ADC, 2Mhz , 600uA - 3.3V
8-bit ADC in 0.35um HHNEC CZ6H process 600uA @ 2Mhz
Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding.
Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32.
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUPIO_01 Library
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Inte…
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications.
512B/ECC16 Nand Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
Standard Definition Video (PAL/NTSC) De-Interlacer, Basic Algorithm
The xc-SDDIB is a low-cost deinterlacing IP core that converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 pr…
Standard Definition Video (PAL/NTSC) De-Interlacer, Advanced Algorithm
The xc-SDDIA core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used …
High-performance Low-memory Mixed Radix FFT
This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT.
1KB/ECC40 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
This is a high performance pipelined implementation of AES optimized for encryption of uncompressed video on low cost FPGA famili…
Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)
Now available up to 170 Mhz per channel !
High Performance DTMB (GB20600-2006) Demodulator Core
Digital demodulator fully supporting GB20600-2006 China DTV standard.
The TC4500 Core complies with DVB-T2 specifications.
Rabbit (TM) 6000 microprocessor
Fifth generation Rabbit Microprocessor
Full-featured 16-bit counter/timer
Full-featured Async/Clocked Serial channel
Dual-channel 8/10 bit Quadrature decoder
Dual-channel 8/10 bit quadrature decoder