Vendor: HCL Technologies Category: Power On Reset (POR)

Power On Reset Circuit

The designated IP is a power on reset circuit intended for integration into 130nm CMOS technology System on Chips.

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Overview

The designated IP is a power on reset circuit intended for integration into 130nm CMOS technology System on Chips. RESET threshold value is determined by 2VTN+VTP over a temperature range of -40 to 120°C. When VDD falls below the reset threshold, RESET goes low and holds the reset signal in high state for 10us after VDD rises above the threshold.

Key features

  • Fully integrated, compact design
  • 3.3V output voltage
  • 3.3V± 10% power supply
  • Area 0.003373mm2
  • CMOS 130nm 1P8M,3.3V IO MOS
  • No external component

Benefits

  • Threshold voltage determined by 2VTN+VTP
  • Fast time to market

What’s Included?

  • GDSII & CDL Netlist
  • .lef for PnR
  • Datasheet
  • Technical Reference Manual, Design Document

Specifications

Identity

Part Number
HCLPOR170310
Vendor
HCL Technologies
Type
Silicon IP

Provider

HCL Technologies
HQ: India
Contact HCL Technologies

Learn more about Power On Reset (POR) IP core

Method for Booting ARM Based Multi-Core SoCs

In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.

Analysis of RDC Paths for a million gate SoC

Reset is necessary to initialize the system and reach to a known state. Just like multiple clocks are required in an SoC to sustain various use models and performance, multiple resets are designed to cater different functional requirements. With this advent we also invite some issues due to crossings among different reset domains. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will become asynchronous crossing path and can cause metastability at destination register.

The silicon enigma: Bridging the gap between simulation and silicon

VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.

BIST Verification at SoC level

With the increase complexity of modern day SoCs, the number of memory blocks and LBIST partitions are increasing, which is in turn making the verification efforts quite challenging. This paper highlights the key points to keep in mind while deciding the verification strategy for self-test, and what are the road-blocks in executing this “ideal” verification plan.

Frequently asked questions about Power-On Reset (POR) IP cores

What is Power On Reset Circuit?

Power On Reset Circuit is a Power On Reset (POR) IP core from HCL Technologies listed on Semi IP Hub.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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