Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to oper…
- MCU
- 10 + 1 years
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to oper…
Video Scaler with Electronic Keystone Correction
The VSC-2 is a high quality polyphase scaler including electronic keystone correction which has been optimized for video and grap…
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium…
Our 6th generation DisplayPort Receiver Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort …
Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPo…
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Behavioral knowledge space combination rule core with parallel operation
So_ip_ecr_bks_p core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Behavioral knowledge space combination rule core with serial operation
So_ip_ecr_bks_s core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification o…
Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the several variants of the Majority Voting combination rule to calculate the ensemb…
So_ip_edte_un_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Area-efficient decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_un_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_smpl_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble classifier inference core
So_ip_idte core can be used create an ensemble of decision trees directly in hardware.
Decision tree evaluation core using serial architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware.
Decision tree evaluation core using pipelined architecture
So_ip_edt_smpl core can be used to implement the decision tree with the previously defined structure directly in hardware.
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.