16-Bit >90dB SNR Stereo Audio DAC with headphone, Mono Audio ADC with microphone, Fujitsu 90nm
The AR34F5G contains a mass-production proven, low power stereo audio DAC and a mono ADC IP for portable multimedia audio applica…
- 16 Bit
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
16-Bit >90dB SNR Stereo Audio DAC with headphone, Mono Audio ADC with microphone, Fujitsu 90nm
The AR34F5G contains a mass-production proven, low power stereo audio DAC and a mono ADC IP for portable multimedia audio applica…
Temperature sensor consists of built-in 10-bit R-2R DAC, diode and own reference voltage former.
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…
Low Jitter Digital PLL – 1.25G/2.5G/5G
The Multiband Quadrature frequency synthesizer generates three frequencies 1.25G / 2.5G / 5G.
IEEE 802.11n/ac/ax (WiFi) LDPC Decoder and Encoder
The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs).
040TSMC_OSC_01 is a CMOS inverter of a Pierce-type variation with an integrated Temperature Compensated Crystal (Xtal) Oscillator…
JESD204B is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between l…
The power on reset consists of a Schmitt trigger and simple logic for forced reset input, whish is forced asynchronous reset.
12-bit 1-channel up to 1 MSPS R/2R DAC
090TSMC_DAC_02 is a 12-bit 1- channel R/2R DAC with sampling rate up to 1 MSPS.
10-bit 1-channel 1 MSPS SAR ADC
090TSMC_ADC_02 is a 10-bit 1-channel successive-approximation register (SAR) analog to digital converter (ADC) circuit with sampl…
14-bit 1-channel 50 MSPS pipeline ADC
This ADC has architecture of pipelined ADC, pipeline ADC consists of a cascade of stages, each stage of the pipeline, excluding t…
LDO voltage regulator (output voltage 2.7 V)
The regulator stabilizes the external voltage (supply voltage) and forms an output level of the specified value.
1.19 V Reference voltage source
Reference voltage source forms temperature-compensated voltage level equal to the width of the band gap of silicon due to mutual …
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast – Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmissio…
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN).
GEO-Mobile Radio (GMR) LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones.
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.
Programmable CMOS PLL high-frequency divider
The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply …
Programmable CMOS PLL high-frequency divider
The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply …
HDTV H.264/AVC Video Encoder with compressed reference frame store
The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm.