Vendor: NTLab Category: Power On Reset (POR)

Power on Reset

The power on reset consists of a Schmitt trigger and simple logic for forced reset input, whish is forced asynchronous reset.

TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

The power on reset consists of a Schmitt trigger and simple logic for forced reset input, whish is forced asynchronous reset. Output port is setRe, that means it is low to set flip-flop in particular state.
The block is fabricated in TSMC SiGe BiCMOS 0.18 um.

Key features

TSMC SiGe BiCMOS 0.18 um
Low current consumption
Small layout area
Portable to other technologies (upon request)

Block Diagram

180TSMC_PoR_01 block diagram

Applications

Power on reset

What’s Included?

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Silicon Options

Foundry	Node	Process	Maturity
TSMC	180nm	BCDG2	Silicon Proven

Specifications

Identity

Part Number

180TSMC_PoR_01

Vendor

NTLab

Type

Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab

HQ: Lithuania

Frequently asked questions about Power-On Reset (POR) IP cores

What is Power on Reset?

Power on Reset is a Power On Reset (POR) IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.