Vendor: Ocean Logic Pty Ltd Category: Video Processing

HDTV H.264/AVC Video Encoder with compressed reference frame store

The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm.

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H.264 / AVC View all specifications

Overview

The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. No DRAM required, thanks to the compressed reference frame store technology.

Simple, fully synchronous and silicon proven design with low gate count.

The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm designed to process HDTV progressive video up to 1920x1080 at 30 fps.

Each block of 16x16 pixels is processed in just 1024 cycles. This means that each pixel is processed in just 4 cycles. Consequently, given an uncompressed video stream of resolution X by Y, and frame rate fps, the minimum clock frequency to process a such video stream is :

F = 4*X*Y*fps

This allows the core to process the video stream at relatively low clock frequencies. For example, HDTV video of 1920x1080 @ 30 fps requires ~250 MHz, whereas VGA video of 640x480 @ 30 fps requires ~37 MHz.

Key features

  • Fully compatible with the ITU-T H.264 specification.
  • Highly (10-15:1 ) compressed frame store (CFS) with perfect reconstruction (no error/drift) with third party standard decoders. Patent pending technology.
  • Extremely low power : no external DRAM required and much lower bandwidth and power through the CFS.
  • I and P frame support.
  • Proven in FPGA : 720p @ 30 fps in Virtex5-2 demo board with video streamed to Ethernet.
  • Profile level 4.1, can be decoded by Baseline, Main or Hi Profile decoder.
  • Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).
  • Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps.
  • Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end device.
  • No CPU required for encoding.
  • Constant Bit Rate (CBR). Partial Variable Bit Rate (VBR).
  • Very low latency (~1.1 ms for VGA @ 30 fps).
  • Motion vector up to –16.00/+15.75 pixels around the predicted motion vector (-24.00/+23.75 around the origin), down to quarter pixel.
  • Support for most of intra4x4 and all intra16x16 modes.
  • Block skipping logic for lower bitrate.
  • Supports YUV 4:2:0 video input.
  • Min Clock speed = ~ 4 x the raw pixel clock speed.
  • Low gate count : 280 Kgates + 217 Kbits of RAM for real time 1080p @ 30
  • Simple, fully synchronous design.
  • Available as fully functional and synthesizable VHDL or Verilog soft-core.

Benefits

  • This core highly compresses (8-16:1) the reference frames. This results in very small storage : ~1 Mbit for 720p, ~2.2. Mbit for 1080p or less.
  • Such small storage can be integrated on the SoC and it allows to eliminate the power hungry external DRAM.
  • Since the data is highly compressed, the compressed frame store memory is rarely accessed, resulting in even more power reduction.
  • Bandwidth is only ~50 Mbytes/s for 1080p@30 .
  • no error or drift is present when decoding with third party H.264 decoders.

Applications

  • Digital video recorders.
  • Video wireless devices.
  • Video surveillance systems.
  • Hand held HDTV video cameras.

What’s Included?

  •  Synthesizable VHDL or Verilog RTL.
  •  Bit accurate C model.
  •  Complete HDL testbench. 
  • Complete data sheet.

Specifications

Identity

Part Number
OL_H264E-CFS
Vendor
Ocean Logic Pty Ltd
Type
Silicon IP

Compute

Codec Standard
H.264 / AVC

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Ocean Logic Pty Ltd
HQ: Australia
Contact Ocean Logic Pty Ltd

Learn more about Video Processing IP core

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An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning

This paper discusses the hardware implementation of an encoder and a decoder for the QOI lossless RGB image format. Some results are given for the AMD/Xilinx architecture, reaching over 800 Mpixels/s in Ultrascale+ and more than 4K@30 in Artix-7. A compression improvement up to ~15% is also observed when natural images are scanned along a Hilbert curve instead of the normal raster order.

Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference

This paper discusses three basic blocks for the inference of convolutional neural networks (CNNs). Pyramid Vector Quantization (PVQ) is discussed as an effective quantizer for CNNs weights resulting in highly sparse and compressible networks. Properties of PVQ are exploited for the elimination of multipliers during inference while maintaining high performance. The result is then extended to any other quantized weights. The Tiny Yolo v3 CNN is used to compare such basic blocks.

A Realtime 1080P30 H.264 Encoder System on a Zynq Device

The Zynq all programmable System On a Chip is a recently introduced device from Xilinx which incorporates two ARM A9 CPU cores, I/O peripherals, memory controller, and programmable logic. This paper describes the implementation of a 1080P30 realtime H.264 encoder system on the device.

Frequently asked questions about Video Processing IP

What is HDTV H.264/AVC Video Encoder with compressed reference frame store?

HDTV H.264/AVC Video Encoder with compressed reference frame store is a Video Processing IP core from Ocean Logic Pty Ltd listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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