The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply …
The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, a prescaler with variable dividing ratio 8/9 and two binary decade counters.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
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Programmable CMOS PLL high-frequency divider is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
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