This ADC has architecture of pipelined ADC, pipeline ADC consists of a cascade of stages, each stage of the pipeline, excluding t…
This ADC has architecture of pipelined ADC, pipeline ADC consists of a cascade of stages, each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (multiplying digital-to-analog converter, MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. This ADC consist of bias, lvds clock receiver, ADC core, output logic correction block. The ADC requires 1.6 ÷ 2 V analog supply and 0.9 ÷ 1.1 V digital supply, there are standby mode which allow to optimize power consumption for system need. Also exist tuning of ADC operating mode by digital correction registers: register ref<3:0> specify differential reference range (refp and refn) , register iadc<2:0> specify tuning of ADC currents, register ish<2:0> specify tuning of sample-and-hold currents, exist possibility to use external voltage source for differential reference refp and refn.
The block is fabricated on TSMC CMOS 0.09 um technology.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 90nm | CIS | Silicon Proven |
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14-bit 1-channel 50 MSPS pipeline ADC is a ADC IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
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