The DisplayPort Multi Stream Transport (MST) Topology Management Software implements MST topology management for multiple monitor…
- Displayport
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The DisplayPort Multi Stream Transport (MST) Topology Management Software implements MST topology management for multiple monitor…
The PWM IP core implements a compact and flexible Pulse Width Modulator.
NetTimeLogic’s NTP Server is a full hardware (FPGA) only implementation of a SNTPv4 Server according to RFC 4330/5905.
NetTimeLogic’s NTP Clientis a full hardware (FPGA) only implementation of a SNTPv4 Client according to RFC 4330/5905.
20b-linear 100MS/s DAC on X-FAB 180nm SOI
20b-linear 100MS/s DAC on X-FAB 180nm SOI
Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
As our connected world expands, the technological advances in high-performance computing (HPC) are reshaping system-on-chip (SoC)…
OPEN Alliance TC14 10BASE-T1S PMD Controller
The CT25207, in combination with the CT25203, implements a OPEN Alliance TC14 10BASE-T1S PMD Interface.
The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port.
Infrastructure for Next-Generation Throughput Demands The Neoverse E1 processor is a new class of efficient CPU technology design…
A Revolution in High Performance Computing The Neoverse V1 CPU is designed to deliver per-core performance on demanding HPC, HPC …
Industry- Performance and Power Efficiency for Cloud-to-Edge Infrastructure Our first Armv9 infrastructure CPU, Neoverse N2 offer…
IoT device security platform with a hybrid post-quantum cryptographic algorithm
QuarkLink™ makes it easy for developers to implement security-by-design for IoT devices.
CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive and provide data to remote Radio E…
The CAN-SEC IP core implements a hardware accelerator for the CANsec extension of the CAN-XL protocol, as defined in CiA’s 613-2 …
MSquare's PCI Express 4.0 PHY IP includes a high-speed, -efficient, and cost-effective transceiver to turbocharge today's high-pe…
Always-on Digital Voice Activity Detection
WhisperTrigger allows your system to detect voice activity and increase its battery life.
Image signal processor to advance vision systems for IoT and embedded markets
The Arm Mali-C55 image signal processor (ISP) is designed to support IoT and embedded applications where energy-efficient, high-q…
PNG Lossless Compression Decoder
The PNG-D core implements a lossless image decompression engine compliant with the Portable Network Graphics (PNG) file format sp…
QOI Lossless Image Compression Decoder
The QOID Core is a decoder that implements a efficient, low-power, lossless image decompression engine compliant with the Quite O…
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.