Vendor: CAST Category: Image Conversion

QOI Lossless Image Compression Decoder

The QOID Core is a decoder that implements a efficient, low-power, lossless image decompression engine compliant with the Quite O…

Overview

The QOID Core is a decoder that implements a highly efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0.

The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity. Capitalizing on the simplicity of the QOI algorithm, the QOID decoder core can decompress images at a very high speed and with minimal silicon resources.

The core occupies approximately 15,000 equivalent NAND2 gates and can decode one pixel per clock cycle. A single core instance can decompress images at rates sufficient for UHD 4k30 video even in low-end FPGAs, 4k60 in mid-range FPGAs, and 8k30 or 60 in modern ASIC technologies.

The QOID core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.

Key features

  • QOI Image Format
    • Lossless compression
    • Supports RGB and RGBA, 8-bit per color images
    • Compression performance similar to that of PNG with a fraction of the computational complexity
  • QOID IP Core 
    • QOI decompression with a compact and high-throughput hardware decoder
    • Receives raw header-less QΟΙ files
      • Optional QOI header processing 
    • Supports RGB images
      • RGBA support can be added on request
  • High-Throughput
    • 1 pixel per clock-cycle throughput 
    • A single core can process UHD 4k60 in mid-range FPGAs, and 8k60 on modern ASIC technologies
  • Compact and Low-Power
    • Approximately 15,000 gates 
  • Deliverables
    • VHDL or Verilog RTL source code or targeted FPGA netlist
    • Verilog can be made available on request 
    • C-model for test vectors generation 
    • Integration Test-Bench 
    • Simulation & synthesis scripts
       

Block Diagram

Specifications

Identity

Part Number
QOID
Vendor
CAST
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Image Conversion IP core

Understanding - and Reducing - Latency in Video Compression Systems

In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. But the meaning of “low latency” can vary, and the methods for achieving low latency aren’t always obvious. Here we’ll define and explain the basics of video latency, and discuss how one of the biggest impacts in reducing latency comes from choosing the right video encoding.

Understanding - and Reducing - Latency in Video Compression Systems

In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting.

Enabling AI Vision at the Edge

Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.

Nextreme Structured ASICs: An alternative for designing cost-optimized ARM926EJ processor-based embedded systems

Traditional IC design options that embedded system designers have had to choose from include fixed hardware devices such as standalone microprocessors, microcontrollers and ASSPs or configurable hardware devices such as FPGAs and cell-based ASICs. In this paper we present a new design option called Nextreme Structured ASICs which provide embedded system designers with a compelling alternative to custom embedded system design.

Frequently asked questions about image conversion IP cores

What is QOI Lossless Image Compression Decoder?

QOI Lossless Image Compression Decoder is a Image Conversion IP core from CAST listed on Semi IP Hub.

How should engineers evaluate this Image Conversion?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Image Conversion IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP