Vendor: Arm Ltd. Category: CPU

Neoverse E1 CPU

Infrastructure for Next-Generation Throughput Demands The Neoverse E1 processor is a new class of efficient CPU technology design…

Overview

Infrastructure for Next-Generation Throughput Demands

The Neoverse E1 processor is a new class of highly efficient CPU technology designed specifically for throughput compute workloads. The design is highly scalable to support throughput demands for next generation edge to core data transport.

Key features

  • Highly Efficient Throughput
    • Simultaneous multithread (SMT) enables Neoverse E1 to execute two threads concurrently resulting in improved aggregate throughput performance. The out-of-order pipeline increases overall performance and offers greater efficiency over its predecessors.
  • Arm Software Ecosystem
    • By supporting the Armv8.2-A architecture and AArch64 ISA, Neoverse E1 is compatible with Neoverse N1, and leverages a broad ecosystem, from tools to OS and application support (e.g. Linux kernel, Data Plane Development Kit and OpenSSL libraries).
  • Highly Scalable Platform
    • Neoverse E1 is a flexible platform which supports scalability from 25Gbps in 4W CPU power budget to multi-100Gbps systems. Accelerator Coherency Port (ACP) enables closely coupled fixed-function hardware offload support with low latency and cache stashing capability.

Block Diagram

Specifications

Identity

Part Number
Neoverse E1
Vendor
Arm Ltd.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Great Britain

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Frequently asked questions about CPU IP cores

What is Neoverse E1 CPU?

Neoverse E1 CPU is a CPU IP core from Arm Ltd. listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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