MACsec Protocol Engine for 10/100/1000 Ethernet
The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standa…
- MACsec
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MACsec Protocol Engine for 10/100/1000 Ethernet
The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standa…
24-bit PDM to PCM 115 dB SNR PLL-less 2 channels
sDSA-SW1.01 is a PDM-PCM converter to interface with a digital microphone.
The agilePVT Sensor Subsystem is a low power integrated macro consisting of Process, Voltage, and Temperature sensors, and associ…
The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking u…
The agilePMU Subsystem is an efficient and integrated Power Management Unit for SoCs/ASICs.
SHA-384 and SHA-512 Secure Hash Crypto Engine
The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash funct…
The agileSensorIF Subsystem is an efficient and integrated sensor interface for SoCs/ASICs.
Controller + ATC + ATS + DTI · RC/EP · x1–x16 · 1 GHz · PCI-SIG certified
Coherent Network-on-chip (NoC) IP
UCIe D2D · CHI Rev E.b · Mesh & Ring · iNoCulator-generated RTL
Non-coherent Network-on-chip (NoC) IP
NC-NOC · AXI4 · Low power · All dies
Low-Power Deeply Embedded RISC-V Processor
The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.
MSquare offers a silicon-proven ONFI 5.0 PHY IP that supports all modes of the Open NAND Flash Interface (ONFI) 5.0 specification.
All self-developed domestic IPs
VeriSyno offers network IP solutions tailored for the high-end server market.
>96 dB over 10 Hz bandwidth,
The Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules.
SpaceFibre and WizardLink Interface
The GRHSSL IP Core is a versatile and configurable high-speed serial link controller written in VHDL, capable of implementing a S…
USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB 2.0 specifications from the USB Implementers Forum and d…
NVMe over TCP IP core - End-to-End NVMe-oF TCP connectivity with no CPU!
NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required.
SMPTE 2110-22 Sub-system (TX/RX) IP-cores for JPEG XS video over RTP encapsulation
The intoPIX SMPTE 2110-22 Sub-system IP-cores (TX & RX) are combining the IPX-RTP-XS cores for JPEG XS RTP packetization / depack…
Video Design Framework for Multi-camera Vision Applications
The logiREF-ACAP-VDF "ACAP IP Framework for Multi-Camera Vision Applications" enables Xylon logiVID-ACAP-6CAM ACAP Vision Develop…