Vendor: Signature IP Corporation Category: Network-On-Chip

Coherent Network-on-chip (NoC) IP

UCIe D2D · CHI Rev E.b · Mesh & Ring · iNoCulator-generated RTL

Overview

The central coherent interconnect fabric for CPUs, AI accelerators, and HBM controllers. CHI Rev E.b compliant. RTL generated by iNoCulator from your PPA targets.

Key specifications

Protocol CHI Rev E.b
Topology Mesh and Ring
RTL source iNoCulator-generated
Sign-off Siemens Questa
Processor IF Arm + RISC-V
Deployment Compute chiplet

Technical details

Master types RN-F · RN-I · RN-D
Slave nodes HN-F · HN-I · SN-F
QoS Configurable per port
Bandwidth Target-driven by iNoCulator
Latency Configurable hops
Verification SystemC + QEMU flows

Key features

  • CHI Rev E.b protocol
  • Mesh and ring topologies
  • Configurable bandwidth & QoS
  • iNoCulator RTL generation
  • Siemens Questa sign-off

Block Diagram

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Specifications

Identity

Part Number
C-NoC
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Learn more about Network-On-Chip IP core

Frequently asked questions about NoC IP cores

What is Coherent Network-on-chip (NoC) IP?

Coherent Network-on-chip (NoC) IP is a Network-On-Chip IP core from Signature IP Corporation listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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