Vendor: Signature IP Corporation Category: Network-On-Chip

Coherent Network-on-chip (NoC) IP

UCIe D2D · CHI Rev E.b · Mesh & Ring · iNoCulator-generated RTL

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Overview

The central coherent interconnect fabric for CPUs, AI accelerators, and HBM controllers. CHI Rev E.b compliant. RTL generated by iNoCulator from your PPA targets.

Key specifications

Protocol CHI Rev E.b
Topology Mesh and Ring
RTL source iNoCulator-generated
Sign-off Siemens Questa
Processor IF Arm + RISC-V
Deployment Compute chiplet

Technical details

Master types RN-F · RN-I · RN-D
Slave nodes HN-F · HN-I · SN-F
QoS Configurable per port
Bandwidth Target-driven by iNoCulator
Latency Configurable hops
Verification SystemC + QEMU flows

Key features

  • CHI Rev E.b protocol
  • Mesh and ring topologies
  • Configurable bandwidth & QoS
  • iNoCulator RTL generation
  • Siemens Questa sign-off

Block Diagram

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Specifications

Identity

Part Number
C-NoC
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Contact Signature IP Corporation

Learn more about Network-On-Chip IP core

HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA

Network-on-Chip (NoC) architectures have become the standard interconnect fabric for many-core systems, yet most proposals face a fundamental trade-off between latency, area, and congestion management. This paper presents HyNoC (Hybrid Network-on-Chip), an open-source NoC architecture that combines circuit-switch path establishment with wormhole data transfer, targeting distributed computing systems built around VLIW processor cores on FPGA.

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures

Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.

Why verification matters in network-on-chip (NoC) design

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Frequently asked questions about NoC IP cores

What is Coherent Network-on-chip (NoC) IP?

Coherent Network-on-chip (NoC) IP is a Network-On-Chip IP core from Signature IP Corporation listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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