The AES-IP-37 (EIP-37) is IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394) up to 6 Gbps.
- AES
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The AES-IP-37 (EIP-37) is IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394) up to 6 Gbps.
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm.
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent tr…
The Watchdog Timer is useful in monitoring the condition where a CPU and software get into an unrecoverable unknown or “stuck” st…
The APB Timer module is a sixteen-bit down counter with a selectable prescaler.
The Real Time Clock (RTC) is a clock-calendar IP core that keeps track of the “Time of Day”.
The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
APB General Purpose IO (w/ interrupt)
The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
The AHB TFT LCD Controller is a configurable core that interfaces to an AHB microprocessor bus and provides all the timing contro…
The interrupt controller monitors interrupts from all other modules within the system and issues interrupt requests to the proces…
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…
The AHB Arbiter arbitrates for the AHB bus among as many as four AHB master components.
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction.
USB4.0 router, Certified USB 5G/10G and 20G Device controller
USB 5G,10G, 20G and 4.0 Device router controller is a configurable core and implements the USB device functionality and can be in…
Digital I/Q Imbalance correction IP for Wireless Applications
The IQE 100 is a wideband imbalance correction IP, that digitally match in-phase and quadrature signal paths in radio architectur…
High-Performance, Configurable, 8-bit Microcontroller
The R8051XC2 configurable processor core implements a range of fast, 8-bit, micro-controllers that execute the MCS®51 instruction…
Common Scrambling Algorithm IP core
The Helion DVB-CSA cores implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide the conditional …
Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs.
cjTAG IEEE 1149.7 Compact TAP Controller
The Compact TAP IP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE …
Super-Speed USB3.0 Hub Controller
USB3.0 SuperSpeed Hub The Super Speed USB bus is implemented as a separate dual-simplex data path consisting of two uni-direction…