Video Scaler with Shrink and Zoom Support
The VSC-1 is a high quality polyphase scaler which has been optimized for video and graphics applications.
- Video Processing
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Video Scaler with Shrink and Zoom Support
The VSC-1 is a high quality polyphase scaler which has been optimized for video and graphics applications.
Display Controller - LCD / OLED Panels (AXI Bus)
The DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconn…
v5.2 Link Layer, Physical Layer, Software Stack and Profiles for Bluetooth low energy
LTIMindtree’s BlueLitE 5.3 IP is a single mode silicon IP consisting of the link layer controller, digital PHY, protocol stack, a…
Ultra low power C-programmable Baseband Signal Processor core
NXP has introduced a new embedded DSP core for ultra low power applications.
Video Processor and Deinterlacer with Line-Doubled Output
The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output.
Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard.
Mil-Std-1553B/AS15531 Interface
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote …
High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from …
Bayer Color Filter Array Interpolation Core
ASICFPGA Bayer CFA Interpolation Core: Digital cameras capture images by using a single sensor with a color filter array.
Lightweight Configurable Display Controller
The IQ-DispLite is a lightweight, fully software configurable display controller IP core.
Quad SPI Flash Memory Controller
The SPI-MEM-CTRL core is an SPI serial NOR and serial NAND flash memory controller, supporting Single, Dual and Quad I/O SPI acce…
Fully Configurable Radix 2 FFT/IFFT Processor
ntFFT core is a fully configurable solution that performs the FFT and IFFT transform.
8/10/12-bit Extended JPEG Encoder with Optional Video Rate Control
The JPEG-E-X core is a standalone and high-performance 8-bit Baseline and 10/12-bit Extended JPEG encoder for still image and vid…
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706,…
The Helion SNOW3G core efficiently implements the stream cipher used as the basis for the UEA2 confidentiality algorithm and UIA2…
Certified USB 5G & 10G Host Controller
USB 5G, 10G Host controller is a configurable core and implements the USB Host functionality that can be interfaced with third pa…
Certified USB 5G & 10G, USB2 Hub controller
USB 5G, 10G and 2.0 Hub controller is a configurable core and implements the USB Hub functionality that can be interfaced with th…
The ntG711_CMP core implements the ITU G.711 compliant compressing.
The AES-IP-39 (EIP-39) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting all NIST modes including …