Certified USB 5G & 10G Dual Mode Controller
USB 5G, 10G Dual Mode controller is a configurable core and implements the USB Host functionality or USB Device functionality sel…
- USB
- FPGA Validated, Demo Available
- Now
- Complaint to xHCI v1.0, USB…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Certified USB 5G & 10G Dual Mode Controller
USB 5G, 10G Dual Mode controller is a configurable core and implements the USB Host functionality or USB Device functionality sel…
I2C Controller IP – Master, Parameterized FIFO, AXI Bus
The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Master, Parameterized FIFO, AHB Bus
The DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mo…
I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to D…
JVC Object-Based Gloss Enhancer
JVC's Object-Based Gloss Enhancer IP, which is already used in its products, is now available for licensing.
USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite int…
Programmable 6-bit CMOS frequency divider
The programmable 6-bit CMOS frequency divider is a set of two independent circuits.
Avalon Multi-port DDR2 Memory Controller
The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in…
12-bit 1-channel 15 to 25 MSPS pipeline ADC
250iHP_ADC_03 is a low-power high-speed 12-bit ADC that employs high-performance differential pipeline architecture.
12-bit 1-channel 10 to 100 MSPS pipeline ADC
250iHP_ADC_02 is a low-power high-speed 12-bit ADC that employs high-performance differential pipeline architecture.
Gen 4 2D (vector graphics) & 3D GPU IP
A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load.
12-bit 2-channel 2.2 MSPS (8.5 kHz BW) delta-sigma ADC
The cell is a second order delta-sigma dual channel (I/Q) analog-to-digital converter that supports sample rates up to 8.5 kHz an…
Digital signal processing has been widely used in the area of sensor devices, smart meter, biometrics, communication, Audio, spee…
Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including …
The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the debug/test capabili…
The TXT_OVERLAY IP Core is a versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RG…