Text Overlay Module (OSD)
The TXT_OVERLAY IP Core is a versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RG…
Overview
The TXT_OVERLAY IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video. The module supports a wide range of text effects and the programming interface is very simple. Text is written to a character buffer which is mapped (via a bitmap ROM) directly to the display.
The characters in the buffer are displayed in a 'text-box' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics.
Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol which is compatible with the popular AMBA AXI4-stream used widely in custom ASICs, FPGAs and SoCs2.
Pixels and syncs are sampled at the module inputs on a rising clock-edge when pixin_val and pixin_rdy are both high. Likewise, pixels and syncs are transferred out of the module on a rising clock-edge when pixout_val is high and pixout_rdy is high.
The pipeline protocol allows both input and output interfaces to be stalled independently if necessary. Any number of text overlay modules may be cascaded in series. By placing more than one overlay module together, the user is able to achieve more complex text and 2D effects.
Key features
- Technology independent soft IP Core for FPGA, ASIC and SoC
- Supplied as human readable VHDL (or Verilog) source code
- Fully pipelined architecture with input/output flow-control and AMBA AXI4-stream compatible data interfaces
- Text overlays/On Screen Displays (OSDs) over RGB video
- Support for RGB pixels in/out (YCbCr formats may be provided on request)
- Real-time programmable character buffer maps instantaneously to the display
- No external memory or frame buffer required
- Supports all video resolutions up to 4096 x 4096 pixels
- Programmable text-box position and size
- Programmable window clipping region
- Independent horizontal and vertical scrolling
- Programmable foreground and background colours
- Programmable 8-bit alpha transparency
- Four sizes of text: 8x16, 16x32, 32x64 or 64x128
- Normal or highlighted text
- Used-defined ROM supports different fonts, characters and custom bitmap graphics
- Ships with four pre-defined character sets
- No complex programming required
- Optional I2C, SPI or UART interfaces for simple programming via micro-processor or micro-controller
- Support for 200 MHz+ operation on basic FPGA devices1 and 500 MHz+ on Ultrascale
Block Diagram
Applications
- Digital TV and home-media solutions including: interactive guides, menus, tables, lists, video games etc.
- Terminal and console windows
- Animated text and graphics such as hardware ‘sprites’, pointers, cursors, buttons etc.
- Window movement in the same manner as a 2D 'BitBlt'
- Scrolling text and moving wrap-around 'banner' displays
- Instrumentation and monitoring applications including animated gauges, charts, dials, meters, counters
What’s Included?
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Video Processing IP
What is Text Overlay Module (OSD)?
Text Overlay Module (OSD) is a Video Processing IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.