Innosilicon Technology Ltd IP Cores

Empowering customers to thrive in the AI Era, INNOSILICON™ introduces its most 112G SerDes (Serializer/Deserializer) and Controll…

• Multi-Protocol PHY

A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device su…

• Root Of Trust

The SAR ADC IP is a small-size, low power analog to digital converter which leverages charge-redistribution successive approximat…

• ADC

The Video DAC IP is designed for transmitting analog video signals from a video source device to a display device, which can be u…

• DAC

The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, ri…

• PLL

The Power-On-Reset (POR) IP provides reliable reset functions for general applications.

• Power On Reset (POR)

The VBO IP is designed for transmitting or receiving video signals between a video source device and display device, which is ful…

• DDR

The PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations.

• PVT Monitor

USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.

• Single-Protocol PHY

USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.

• Single-Protocol PHY

The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…

• UCIe

The MIPI D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimedia…

• MIPI PHY

The Image Signal Processing (ISP)-- ISI700 receives camera sensor data via the 4-channel DVP interface.

• ISP Image Signal Processor

The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wid…

• SD / eMMC Controller

The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devi…

• Displayport

The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring acces…

• Single-Protocol PHY

The ONFI IP provides Turnkey solutions for IC requiring access to ONFI-compatible NAND Flash devices.

• DDR

The’s I3C (Improved Inter Integrated Circuit) is enhanced with I2C protocol and is compatible with I2C.

• I2C / I3C

The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …

• Multi-Protocol PHY

The GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode.

• DDR