SENT Protocol IP Core for Automotive Communication
The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller.
- SENT
Low-Speed Control Interface IP cores provide the communication, control, monitoring, and management functions required by modern SoCs, microcontrollers, automotive systems, industrial equipment, and embedded platforms. These interfaces enable reliable connectivity between processors, sensors, peripherals, power-management devices, and external subsystems.
This catalog includes IP solutions for widely adopted control and management protocols such as I2C/I3C, SPI/QSPI/xSPI, UART, CAN, CAN FD, CAN XL, LIN, GPIO, IEEE 1588/PTP, MIPI RFFE, PMBus, Smartcard, ARINC 429, MIL-STD-1553, FlexRay, SENT, HDLC, and other specialized interfaces. Compare controller, target, and protocol IP offerings from multiple vendors based on standards compliance, feature sets, safety support, performance, and integration requirements.
SENT Protocol IP Core for Automotive Communication
The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller.
UHF RFID EPC Gen2V2 physical interface
180SMIC_G2PHY_01 is an IP intended for use in passive UHF transponder applications.
UHF RFID EPC Gen2 physical interface
130GF _G2PHY_02 is the IP intended for use in passive UHF transponder applications.
Pulse Per Second (PPS) Clock to PPS core
NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configura…
MIPI I3C Slave v1.1 Controller IP enables efficient data flow for sensor integration.
As Sensor data rate increases, there is a necessity to have control information flowing to and from sensors at an efficient data …
I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products, compliant with …
ARINC 429 IP-Core with DO-254 Package
The ARINC-429 IP Core is a multi-channel ARINC 429 transmitter and receiver core for serial communication in airborne application…
SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
UHF RFID EPC Gen2 physical interface
130GF_G2PHY_01 is the IP intended for use in passive UHF transponder applications.
Our efficient Core performs serial-to-parallel conversion on data received from a IR Receiver Diode.
I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmissio…
I2C Bus Master / Slave Controller Interface with FIFO
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmissio…
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DC…
NMEA Time of Day (ToD) Slave core
NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to …
NMEA Time of Day (ToD) Master core
NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to syn…
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an…
NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize othe…
Pulse Per Second Master (PPS) core
NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Pulse Per Second Slave (PPS) core
NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a P…