eMMC/SD/SDIO Combo IP

The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of applications. This IP integrates a host controller and PHY, enabling seamless communication with eMMC, SD, and SDIO devices. When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes.

With its robust architecture and compliance with industry standards (such as JESD84-B51 eMMC5.1 specifications, SD3.01 specifications, and SDIO3.00 specifications), this IP is ideal for applications requiring high-speed data transfer, low power consumption, and reliable connectivity.

• Compliant with eMMC5.1 specifications, up to 200MHz
• Supports HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
• Supports Enhanced Strobe in HS400
• Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
• Supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed mode
• Supports adjusting the CMD/CLK/DAT IO Driver Strength
• Supports power sequence-free operations
• Supports open drain applications
• ESD protection for I/O signal
• Supports Built-In Self-Test
• Supports VDDQ 3.3V/1.8V

• High capacity
• High speed
• High compatibility

• Databook
• Integration and Simulation Guide
• Detailed physical implementation guides for the complete PHY
• Library Exchange Format (LEF) file with pin size and locations
• Gate-level netlist and Standard Delay Format (SDF)Timing file
• Encrypted Verilog Models
• Layout Versus Schematic (LVS) flattened netlist and report
• Design Rule Check (DRC) report
• GDSII database for foundry merge
• Optional backend integration