LunaNet AFS LDPC Encoder and Decoder IP Core
The IP Core implements LunaNet LDPC code for Lunar Augmented Navigation Services.
- Channel Coding
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
These IP cores accelerate compute-intensive workloads such as AI and machine learning, signal processing, video and image processing, cryptography, and data analytics.
This catalog allows you to explore and compare compute IP cores from leading vendors based on performance, power efficiency, flexibility, and process node compatibility.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
LunaNet AFS LDPC Encoder and Decoder IP Core
The IP Core implements LunaNet LDPC code for Lunar Augmented Navigation Services.
WAVE-N is a high-performance, video-specialized NPU IP designed to deliver real-time, deep learning-based image enhancement for e…
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The FH-OFDM modem is developed for OFDM applications used in frequency hopping transmission scenarios or fixed frequency scenario…
The NAVIC BCH decoder is developed for satellite navigation applications.
The NR-5G Polar encoder/decoder is developed for 5G new radio.
OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-sour…
DVB-S2X Wideband LDPC/ BCH Encoder
The DVB-S2X Wideband LDPC BCH Encoder IP Core is developed for Digital Video Broadcasting applications.
The ASRC core is a compact and high-performance audio sample rate converter.
High-Performance Memory Expansion IP for AI Accelerators
AI inference performance is increasingly constrained by memory bandwidth and capacity - not compute.
Fixed Point Doppler Channel IP core
The Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase …
InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor.
The Cache MX IP compresses on-chip L2, L3 SRAM cache enabling 2x effective capacity.
InCore Azurite is an extremely compact, RISC-V 2-stage pipelined micro-processor.
Fast Fourier Transform IP Core
The Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algo…
Highly scalable inference NPU IP for next-gen AI applications
The inference neural processing unit (NPU) IP is suitable for high-performance edge devices including automotive, cameras, and mo…
(2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
The LDPC IP is a specialized encoder and decoder for Low-density parity-check codes, specifically designed for the 802.3an standa…
ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where…
ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
The Synopsys ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost …
The ZIA™ A3000 AI processor IP is a low-power processor specifically designed for edge-side neural network inference processing.