HMAC-SHA256 cryptographic accelerator
The HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes.
- SHA2 (SHA-256)
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
HMAC-SHA256 cryptographic accelerator
The HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes.
MACsec Protocol Engine for 10/100/1000 Ethernet
The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standa…
SHA-384 and SHA-512 Secure Hash Crypto Engine
The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash funct…
Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
As our connected world expands, the technological advances in high-performance computing (HPC) are reshaping system-on-chip (SoC)…
IoT device security platform with a hybrid post-quantum cryptographic algorithm
QuarkLink™ makes it easy for developers to implement security-by-design for IoT devices.
The CAN-SEC IP core implements a hardware accelerator for the CANsec extension of the CAN-XL protocol, as defined in CiA’s 613-2 …
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
PCIe 5.0 Integrity and Data Encryption Security Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to …
Media Access Control Security (MACSec)
Media Access Control Security (MACSec) is an IEEE standards-based protocol for securing communication among the trusted component…
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engine…
IEC 61850/62351 Substation Automation Systems Cryptographic IP Core
IEC 61850/62351 Substation Automation Systems Cryptographic (SASCrypt) IP Core secures the strict real-time traffic used in the S…
AES-XTS Storage Encrypt/Decrypt Engine
The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data.
The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data.
The Beyond SHA-3 is a high-throughput, area-efficient hardware implementation of the SHA-3 cryptographic hashing functions, compl…
SHA-3 Secure Hash Crypto Engine
The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to N…
256-bit SHA Secure Hash Crypto Engine
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256.
Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores.
AES-CCM Authenticated Encrypt/Decrypt Engine
The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.