Vendor:
Synopsys, Inc.
Category:
PCIe / CXL IDE
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
Overview
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads.
The CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification for the CXL.io protocol. The CXL 2.0 IDE Security Module integrates seamlessly with the CXL controllers to accelerate SoC integration.
The CXL 2.0 IDE Security Module supports full-duplex for .cache/.mem and .io Rx and Tx directions. It provides efficient encryption/decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed to meet an optimal area vs. performance implementation.
Key features
- Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
- Compliant with PCI Express IDE specification for CXL.io
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with the Controller IP
- FLIT interfacing for CXL.cache/mem
- TLP packet-based interfacing for CXL.io
- Sync/fail/status messaging
- Supports CXL 2.0 data rates
- Customer configurable
- Aligns with the CXL 2.0 Controller configuration options
- Data bus width: 512
- Lanes: x8, x16
- Support for all protocols CXL.cache/mem/io or only CXL.cache/mem
- CXL.cache/mem
- Containment & skid modes
- Early MAC termination
- Support for TDISP
- Optimized for area, performance & latency
- Multi-stream support
- PCRC calculation & validation
- Efficient key control & refresh
- Bypass mode
Block Diagram
dwc_cxl_2_ide_security_module block diagram
Specifications
Identity
Part Number
dwc_cxl_2_ide_security_module
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about PCIe / CXL IDE IP cores
What is CXL 2.0 Integrity and Data Encryption Security Module?
CXL 2.0 Integrity and Data Encryption Security Module is a PCIe / CXL IDE IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this PCIe / CXL IDE?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCIe / CXL IDE IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.