Memory Interface IP Cores

DDR4 Memory Model provides an smart way to verify the DDR4 component of a SOC or a ASIC.

• Controller
• DDR4

DDR3L Memory Model provides an smart way to verify the DDR3L component of a SOC or a ASIC.

• Controller
• DDR3

DDR3 DIMM Memory Model provides an smart way to verify the DDR3 DIMM component of a SOC or a ASIC.

• Controller
• DDR3

DDR3 3DS Memory Model provides an smart way to verify the DDR3 3DS component of a SOC or a ASIC.

• Controller
• DDR3

DDR3 Memory Model provides an smart way to verify the DDR3 component of a SOC or a ASIC.

• Controller
• DDR3

DDR2 Memory Model provides an smart way to verify the DDR2 component of a SOC or a ASIC.

• Controller
• DDR2

DDR Memory Model provides an smart way to verify the DDR component of a SOC or a ASIC.

• Controller

Serial_Flash Controller interface provides full support for the two-wire Serial_Flash Controller synchronous serial interface,com…

• Controller

LPDDR4 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR4 JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C,…

• Controller
• LPDDR4

LPDDR3 interface provides full support for the LPDDR3 interface, compatible with JESD209-3,JESD209-3B and JESD209-3C specificatio…

• Controller

LPDDR2 interface provides full support for the LPDDR2 interface, compatible with JESD209-2E and JESD209-2F specification and DFI-…

• Controller

LPDDR is full-featured, easy-to-use, synthesizable design, compatible with JESD209A-1 and JESD209B specification and DFI-version …

• Controller

DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.…

• Controller + PHY + 1
• LPDDR5

SDRAM Assertion IP provides an efficient and smart way to verify the SDRAM designs quickly without a testbench.

• Controller

LPDDR5X Assertion IP provides an efficient and smart way to verify the LPDDR5X designs quickly without a testbench.

• Controller
• LPDDR5X

LPDDR5 Assertion IP provides an efficient and smart way to verify the LPDDR5 designs quickly without a testbench.

• Controller
• LPDDR5

LPDDR4 Assertion IP provides an efficient and smart way to verify the LPDDR4 designs quickly without a testbench.

• Controller
• LPDDR4

LPDDR3 Assertion IP provides an efficient and smart way to verify the LPDDR3 designs quickly without a testbench.

• Controller

DFI LPDDR Assertion IP provides an smart way to verify the ARM DFI LPDDR component of a SOC or a ASIC.

• Controller

DFI HBM2E Assertion IP provides an efficient and smart way to verify the DFI HBM2E designs quickly without a testbench.

• Controller