Serial Flash Controller IIP

Serial_Flash Controller interface provides full support for the two-wire Serial_Flash Controller synchronous serial interface,compatible with Serial_Flash Controller specification. Through its Serial_Flash Controller compatibility, it provides a simple interface to a wide range of low-cost devices. Serial_Flash Controller IIP is proven in FPGA environment.The host interface of the Serial_Flash Controller can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Serial Flash Controller IIP is supported natively in Verilog and VHDL

• Compliant with Flash Devices from major Flash Device Vendors.
• Full Flash with SPI Master Functionality.
• Supports 3 modes of operation
• Slave Mode - Accessing flash device through CSR registers from SOC Slave interface
• XIP Mode - eXecute In-Place, where core allows direct access to flash memory from SOC Slave interface.
• HCI Mode - Descriptor based DMA type access from SOC Master Interface.
• Supports xSPI (JEDEC’s JESD251), Xccela and Optional Hyperbus standard
• Supports 3 wire and 4 wire operation
• Supports DDR mode of operation
• Single, dual, quad and octal serial data lines
• In built DMA (Host Controller Interface) controller
• Boot image copy Support after power on reset.
• Up to 16 slaves supported under master control
• Mode fault error flag with CPU interrupt capability
• Serial clock with programmable polarity and phase
• LSB or MSB mode
• Supports flexible Serial clock generation
• Full duplex and half duplex operation
• Supports any kind of SPI transactions to access any kind of SPI slave device
• Thresholds to generate interrupt.
• Software and Hardware Reset.
• Control and Status Registers to configure the module
• Configurable Transmit/Receive Data FIFO.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The Serial_Flash Controller interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed, VHDL and SystemC can also be provided
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and linux driver package
• Documentation contains User's Guide and Release notes.