DDR2 Memory Model

DDR2 Memory Model provides an smart way to verify the DDR2 component of a SOC or a ASIC. The SmartDV's DDR2 memory model is fully compliant with standard DDR2 Specification and provides the following features. Better than Denali Memory Models.

DDR2 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR2 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports DDR2 memory devices from all leading vendors.
• Supports 100% of DDR2 protocol standard JESD79-2F.
• Supports all the DDR2 commands as per the specs.
• Supports double data rate interface.
• Supports upto 4 GB device density.
• Supports 8 internal banks.
• Supports the following devices.
• X4
• X8
• X16
• Supports all speed grades as per specification.
• Quickly validates the implementation of the DDR2 standard JESD79-2F.
• Supports Programmable Write latency and Read latency.
• Supports Programmable burst lengths: 4,8.
• Supports the following burst types.
• Sequential
• Interleave
• Supports for burst sequence.
• Checks for following
• Check-points include power up,initialization and power off rules
• State based rules, Active Command rules
• Read/Write Command rules etc.,
• All timing violations
• Supports for All Mode registers programming.
• Supports for Extended Mode registers programming.
• Supports for Write data Mask.
• Supports for Power Down features.
• Supports for Self Refresh mode.
• Supports Auto precharge option for each burst access.
• Supports for input clock stop and frequency change.
• Supports for ODT(On-Die Termination).
• Supports for DLL.
• Supports for full-timing as well as behavioral versions in one model.
• Supports for all timing delay ranges in one model: min, typical and max.
• Constantly monitors DDR2 behavior during simulation.
• Protocol checker fully compliant with DDR2 Specification JESD79-2F.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of DDR2 designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the DDR2 testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.