Vendor: SmartDV Category: LPDDR

LPDDR3 Assertion IP

LPDDR3 Assertion IP provides an efficient and smart way to verify the LPDDR3 designs quickly without a testbench.

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Overview

LPDDR3 Assertion IP provides an efficient and smart way to verify the LPDDR3 designs quickly without a testbench. The SmartDV's LPDDR3 Assertion IP is fully compliant with standard LPDDR3 Specification.

LPDDR3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports all signal level checks including X detection
    • Support for check-points include power on, Initialization and power off rules,
    • Support for state based rules, Active Command rules,
    • Support for Read/Write Command rules etc.
    • Support for all timing violations.
    • Supports all legal data and address widths configuration
    • Supports different Read/write latency
    • Supports power down and deep power down
    • Supports clock stop feature
    • Supports mode register command period configurability
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR3 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR3 Assertion IP functionality.

Block Diagram

LPDDR3 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPDDR3 AIP
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

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Frequently asked questions about LPDDR Interface IP

What is LPDDR3 Assertion IP?

LPDDR3 Assertion IP is a LPDDR IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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