DDR3 DIMM Memory Model

DDR3 DIMM Memory Model provides an smart way to verify the DDR3 DIMM component of a SOC or a ASIC. The SmartDV's DDR3 DIMM memory model is fully compliant with standard DDR3 DIMM Specification and provides the following features. Better than Denali Memory Models.

DDR3 DIMM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR3 DIMM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports DDR3 DIMM memory devices from all leading vendors.
• Supports 100% of DDR3 DIMM protocol standard.
• Supports DDR3 UDIMM, RDIMM and LRDIMM types.
• Supports all the DDR3 DRAM features.
• Supports up to 32 GB device density.
• Supports 8 internal banks.
• Supports the following devices.
• X4
• X8
• X16
• Supports all speed grades as per specification.
• Supports ECC error detection and correction.
• Supports Single, Dual and Quad ranks.
• Supports fixed burst chop (BC) of 4 and burst length (BL) of 8.
• Supports BC4 or BL8 on-the-fly (OTF).
• Supports Fly-by topology.
• Supports Parity operations.
• Checks for following
• Check-points include power up, initialization and power off rules
• State based rules, Active Command rules
• Read/Write Command rules etc.,
• All timing violation
• Quickly validates the implementation of the DDR3 DIMM standard.
• Protocol checker fully compliant with DDR3 DIMM Specification.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Constantly monitors DDR3 DIMM behavior during simulation.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of DDR3 DIMM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the DDR3 DIMM testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.