LPDDR Controller IIP

LPDDR is full-featured, easy-to-use, synthesizable design, compatible with JESD209A-1 and JESD209B specification and DFI-version 2.0 or higher specification Compliant. Through its LPDDR compatibility, it provides a simple interface to a wide range of low-cost devices. LPDDR IIP is proven in FPGA environment. The host interface of the LPDDR can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

LPDDR Controller IIP is supported natively in Verilog and VHDL

• Supports LPDDR protocol standard and JESD209A-1 and JESD209B Specification
• Compliant with DFI version 2.0 or higher Specification.
• Supports up to 16 AXI ports with data width upto 512 bits.
• Supports controllable outstanding transcations for AXI write and read channels
• Supports in port arbitration and multi port arbitration.
• Supports user programmable page policy.
• Closed page policy
• Open page policy
• Supports Error Checking and correction (ECC).
• Supports retry on ECC error, with retry limit user controllable.
• Supports high clock speeds in ASIC and FPGA.
• Supports low latency for write and read path.
• Supports reordering of transcations for higher performance.
• Supports up to 2GB device density
• Supports X32 and X16 devices
• Supports all speed grades as per specification
• Supports programmable CAS latency
• Supports programmable burst length: 2, 4, 8 and 16
• Supports Mode registers/Control programming
• Supports extended mode register programming
• Supports burst type: Sequential and Interleave
• Supports burst order
• Supports write data mask
• Supports power down features
• Supports deep power down features
• Supports auto precharge option for each burst access
• Supports auto refresh and self refresh modes
• Supports Multiple Outstanding transaction
• Supports In-port Arbitration using QoS
• Supports 2:1 and 4:1 Clock Ratio Modes
• Supports CRC and ECC for Write and Read Operations
• Supports 1:4 Controller to DFI PHY frequency ratio
• Supports Programmable clock frequency operation
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The LPDDR interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User's Guide and Release notes.