Vendor: SmartDV Category: LPDDR

LPDDR4 Assertion IP

LPDDR4 Assertion IP provides an efficient and smart way to verify the LPDDR4 designs quickly without a testbench.

Controller LPDDR4 View all specifications

Overview

LPDDR4 Assertion IP provides an efficient and smart way to verify the LPDDR4 designs quickly without a testbench. The SmartDV's LPDDR4 Assertion IP is fully compliant with standard LPDDR4 Specification.

LPDDR4 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR4 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports 100% of LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y(Proposed).
    • Supports all the LPDDR4 commands as per the specs.
    • Quickly validates the implementation of the LPDDR4 standard JESD209-4,JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
    • Supports for all mode registers programming.
    • Supports for Programmable READ/WRITE Latency timings.
    • Supports for both 16 and 32 Programmable burst lengths.
    • Supports for the following Burst Type,
    • Sequential
    • Supports for Burst sequence.
    • Checks for following
    • Check-points include power up,initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports for Write data mask and data strobe features.
    • Supports for Write and Read DBI.
    • Supports for Write leveling.
    • Supports for CA training.
    • Supports for ODT(On-Die Termination) features.
    • Supports for ZQ Calibration commands.
    • Supports for DQ Calibration.
    • Supports for DQ Vref training.
    • Supports for Byte mode.
    • Supports for Power Down features.
    • Supports for Self refresh.
    • Supports for Refresh management.
    • Supports for all types of timing and protocol violation detection.
    • Supports for full-timing as well as behavioral versions in one model.
    • Supports for all timing delay ranges in one model: min, typical and max.
    • Protocol checker fully compliant with LPDDR4 Specification JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
    • Constantly monitors LPDDR4 behavior
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR4 Assertion IP functionality.

Block Diagram

LPDDR4 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPDDR4 AIP
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Standards & Interfaces

Memory
LPDDR4

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about LPDDR IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about LPDDR Interface IP

What is LPDDR4 Assertion IP?

LPDDR4 Assertion IP is a LPDDR IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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