Vendor: SmartDV Technologies Category: DDR

SDRAM Assertion IP

SDRAM Assertion IP provides an efficient and smart way to verify the SDRAM designs quickly without a testbench.

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Overview

SDRAM Assertion IP provides an efficient and smart way to verify the SDRAM designs quickly without a testbench. The SmartDV's SDRAM Assertion IP is fully compliant with standard SDRAM Specification.

SDRAM Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SDRAM Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports SDRAM memory devices from all leading vendors.
    • Supports 100% of SDRAM protocol standard 512Mb_sdr & HY57V56820FT-H
    • Supports Internal banks for hiding row access/precharge
    • Supports Programmable burst lengths: 1, 2, 4, 8, or full page
    • Supports Auto-precharge, includes concurrent auto precharge and auto refresh modes
    • Supports Self refresh mode
    • Supports Auto refresh
    • Supports all types of timing and protocol violation detection
    • Supports All Mode registers programming
    • Supports following Speed Grade
    • 7E
    • 75
    • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Commands rules etc.
    • All timing violations.
    • Bus-accurate timing for min, max and typical values
    • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
    • Constantly monitors SDRAM behavior during simulation
    • Protocol checker fully compliant with 512Mb_sdr & HY57V56820FT-H
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV SDRAM VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure SDRAM Assertion IP functionality.

Block Diagram

SDRAM AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
SDRAM AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is SDRAM Assertion IP?

SDRAM Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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