TSMC IP Cores

A Fail-Safe Digital I/O Library.

• TSMC
• 28nm

A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells an…

• TSMC
• 16nm

A Wirebond and FlipChip compatible

• TSMC
• 28nm

A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.

• TSMC
• 65nm
• GP

A TSMC 130nm Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O.

• TSMC
• 130nm
• BCD/BCD+

A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associ…

• TSMC
• 22nm
• ULL

A TSMC 28nm Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, with Specialized RF Wirebond Cells for LNAs.

• TSMC
• 28nm

A 2Gbps differential transceiver.

• TSMC
• 16nm

IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.

• Controller + PHY + 1
• TSMC
• 7nm
• N7FF

High end consumer and professional applications require crystals with a minimum number of external components.

• TSMC
• 7nm
• N7FF

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 80nm
• GC

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 5nm
• N5A

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 55nm
• GP

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 3nm
• N3E

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 2nm
• N2P

The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multipli…

• TSMC
• 16nm
• FFC

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• PHY
• TSMC
• 28nm
• HPC
• Available on request

The Glitch Detector macro comprehensively addresses typical SOC power supply and other voltage glitch monitoring needs in a fully…

• TSMC
• 3nm
• N3E

The Glitch Detector macro comprehensively addresses typical SOC power supply and other voltage glitch monitoring needs in a fully…

• TSMC
• 2nm
• N2P

The Droop Detector macro addresses SOC power supply and other voltage droop monitoring needs in a fully integrated easy-to-use ma…

• TSMC
• 5nm
• N5