Neuromorphic Processor IP (Second Generation)
Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.
- Edge AI Accelerator
- now
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Neuromorphic Processor IP (Second Generation)
Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.
The K-best decoder is part of the MIMO decoder.
DeepMentor has developed an AI IP that combines low-power and high-performance features with the RISC-V SOC.
AXI Performance Subsystem - ARM Cortex A
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needin…
The XC21 is the most efficient vector DSP core available today for communications applications.
Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee.
eFPGA on GlobalFoundries GF12LP
All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee.
Nand Flash write cycles are limited.
LDPC (1723,2048) core is compliant with IEEE Standard 802.3.2018 Ethernet specification.
FEC RS (544,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD…
FEC RS (528,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD…
FEC RS (255,251) core is compliant with standard HDMI 2.1/2.1a and Scalabale Low Voltage Signaling with Embedded Clock (SLVS_EC) …
FEC RS (254,250) core is compliant with standard VESA Display Port version 1.4/2.0/2.1.
FEC RS (198,194) core is compliant with standard Universal Serial Bus 4 Specification and standard VESA Display Port version 2.0/…
The RI5CY Verification IP provides an effective & efficient way to verify the components interfacing with RI5CY bus of a PULP mic…
The FPU Verification IP provides an effective & efficient way to verify the components interfacing with FPU interface with a RISC…
The TT-Ascalon™ is an Out-of-Order, superscalar, 8-wide decode processor based on the RISC-V RVA23 profile, co-designed and optim…
High-performance AI dataflow processor with scalable vector compute capabilities
The new XM Series offers an extremely scalable and efficient AI compute engine.
The Ceva-NeuPro-Nano is a efficient and self-sufficient Edge NPU designed for Embedded ML applications.
LDPC Decoder for 5G NR and Wireless
The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal p…